As integrated circuit semiconductor technology continues to scale to smaller geometries, intrinsic threshold voltage (Vt) variations in minimum geometry size affect quality. For example, the static noise margin (SNM) in a complementary metal-oxide semiconductor (CMOS) static random-access memory (SRAM) cell can be adversely affected by intrinsic Vt variations. This reduction in SNM caused by increasingly smaller transistor geometries can cause difficulties. SNM is further reduced when Vcc is scaled to a lower voltage.
The Vt variations pose barriers to the scaling of supply voltage, transistor size, and, hence, the minimum six transistor (6T) CMOS SRAM cell size. These barriers limit the total transistor yield for conventional 6T SRAM-dominated high performance CMOS devices such as application-specific integrated circuits (ASICs) and microprocessors due to die size and cost constraints.